[AVR] MCU Control Register

MCU Control Register – MCUCR

 

Bit	7	6	5	4	3	2	1	0
	SRE	SRW10	SE	SM1	SM0	SM2	IVSEL	IVCE
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial Value	0	0	0	0	0	0	0	0

 

Bit 7 – SRE: External SRAM/XMEM Enable

Writing SRE to one enables the External Memory Interface.The pin functions AD7:0,

A15:8, ALE, WR, and RD are activated as the alternate pin functions. The SRE bit overrides

any pin direction settings in the respective data direction registers. Writing SRE to

zero, disables the External Memory Interface and the normal pin and data direction settings

are used.

 

Bit 6 – SRW10: Wait-state Select Bit

For a detailed description in non-ATmega103 compatibility mode, see common description

for the SRWn bits below (XMCRA description). In ATmega103 compatibility mode,

writing SRW10 to one enables the wait-state and one extra cycle is added during

read/write strobe as shown in Figure 14.